Careers at Samplify
Samplify takes pride in employing the best individuals in the industry.
If you would like to join our team, please email your resume to:
Current Openings:
Lead ASIC/System Design Engineer:
Seeking ASIC/System Design Engineer with breadth of experience ranging from HDL design and development, verification, testbench infrastructure, to FPGA based board/system bring up. Ability to write a comprehensive functional/design specifications. Candidate will have responsibilities in all aspects of the product development life cycle: design, verify, synthesize for FPGA and ASIC, and integration with end customer systems. Requires thorough knowledge of C/C++, SystemC, Verilog, Python, and FPGA technologies. Ability to lead a design team. Experience with DSP based design, ASIC Back End and Board Design are a plus. Minimum seven years relevant experience is required.
Senior ASIC/System Design Engineer:
Seeking ASIC/System Design Engineer with breadth of experience ranging from HDL design and development, verification, testbench infrastructure, to FPGA based board/system bring up. Candidate will have responsibilities in all aspects of the product development life cycle: design, verify, synthesize for FPGA and ASIC, and integration with end customer systems. Requires thorough knowledge of C/C++, SystemC, Verilog, Python, and FPGA technologies. Experience with DSP based design, ASIC Back End and Board Design are a plus. Minimum five years relevant experience is required.
Lead ASIC Verification Engineer:
Seeking ASIC Verification Engineer with experience across the entire ASIC design/verification cycle. Verification at the C++/SystemC Model level, RTL level, Gate Level, FPGA platform, and ATE functional test development. Ability to write a comprehensive test plan from functional specifications. Required skills include C++/SystemC, Assertions, Verilog, Python, Shell Scripting, and Make. Focus on metrics based verification using coverage and assertions. Ability to lead a verification team. Experience with DSP based design, embedded SW, and FPGA are a plus. Minimum seven years relevant experience is required.
Senior ASIC Verification Engineer:
Seeking ASIC Verification Engineer with experience across the entire ASIC design/verification cycle. Verification at the C++/SystemC Model level, RTL level, Gate Level, FPGA platform, and ATE functional test development. Ability to create a test plan from functional specifications. Required skills include C++/SystemC, Assertions, Verilog, Python, Shell Scripting, and Make. Focus on metrics based verification using coverage and assertions. Experience with DSP based design, embedded SW, and FPGA are a plus. Minimum five years relevant experience is required.
